1. Field of the Invention
The present invention relates generally to redundant memory and, more particularly, to a two-bit prefetch scheme in a redundant memory system.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device which is coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. Memory manufacturers provide an array of innovative fast memory chips for various applications. While both Dynamic Random Access Memories (DRAM) and Static Random Access Memories (SRAM) are making significant gains in speed and bandwith, even the fastest memory devices cannot match the speed requirements of most microprocessors.
Another type of memory device is a standard Synchronous Dynamic Random Access Memory (SDRAM). Synchronous control means that the DRAM latches information from the processor under the control of the system clock. The processor can be told how many clock cycles it takes for the DRAM to complete its task so it can safely implement other tasks while the DRAM is processing its request. Regardless of the type of memory, the solution for providing adequate memory bandwith depends on system architecture, the application requirements, and the processor, all of which help determine the best memory type for a given application. Limitations on speed include delays in the chip, the package, and the system. Thus, significant research and development has been devoted to finding faster ways to access memory.
Because microprocessor technology enables current microprocessors to operate faster than current memory devices, techniques for increasing the speed of memory devices are often implemented. One technique for increasing the speed of a SDRAM is called a xe2x80x9cprefetch.xe2x80x9d In a prefetch system, more than one data word is fetched from the memory on each address cycle. The data may be temporarily stored in a buffer. Multiple words of data can then be sequentially clocked out for each address access. The main advantage of this approach is that for any given technology data can be accessed in multiples of the internal clock rate of the DRAM.
In a Double Data Rate (DDR) memory, the data transfer rate is twice that of a regular SDRAM because the DDR""s I/O data can be strobed twice for every clock cycle. Thus, data is sent on both the rising and falling edge of the clock signal rather than just the rising edge of the clock signal as in typical Single Data Rate (SDR) systems. With the increase of data output bandwith, DDR provides a method of doubling the data rate of the memory device. In implementing DDR, two bits or segments are prefetched and stored at a single column address. Generally, the operational speed of the memory device in the two bit prefetch method is doubled, and the data is temporarily stored in a latch circuit. Each segment of data is processed on either the rising or falling edge of the clock signal. Since two segments of data for a single column address are prefetched with each clock cycle, the data may be defined and stored in two locations corresponding to a single column address. This may be referred to as xe2x80x9cleftxe2x80x9d and xe2x80x9crightxe2x80x9d data or, alternatively, as xe2x80x9cevenxe2x80x9d and xe2x80x9coddxe2x80x9d data for a single column address.
Another area of memory technology that has been improved is memory fault protection. When a memory device such as an SDRAM is manufactured, there may be various anomalies in various memory cells of the device. During electrical testing of a memory device at the manufacturer, faulty memory cells may be detected. To minimize the impact of such failures, redundant row and column segments are often provided to replace the normal memory addresses detected as faulty during electrical testing. A redundant memory row or column circuit typically includes a set of programmable fuses, one for each address bit. When a fault is detected in a cell of the original memory array, fuses can be programmed to provide access to one of the redundant rows or columns. This will provide a replacement cell from a redundant array for the faulty cell in the original memory array. Conversely, antifuses may be used to open paths to the faulty memory cells. Disadvantageously, fuses are fairly large and require additional space on the memory device.
When combining redundant memory technology with DDR SDRAM technology, fuses may be used for each segment (LEFT/RIGHT) of each column address to provide a path for the possible implementation of a redundant memory circuit. Disadvantageously, fuses are comparatively large and take up valuable real estate which may be used for memory storage. Because memory real estate may be at a premium, it would be advantageous to implement the advances used in DDR SDRAM technology and redundant memory technology while minimizing the circuitry associated with the advanced DDR SDRAM and redundancy technologies.
The present invention may address one or more of the problems set forth above.